发明名称 SEDC-BASED ERROR DETECTION APPARATUS FOR PROGRAMABLE ADD/SUBSTRACT OPERATIONS UNIT AND SELF-CHECKING PROGRAMMABLE ADD/SUBSTRACT OPERATIONS UNIT HAVING THE APPARATUS
摘要 PURPOSE: An error detection device based on SEDC(Scalable Error Detection Coding) for a programmable addition/subtraction operation unit and a self-checking programmable addition/subtraction operation unit which includes the error detection device are provided to enable an input SEDC generator and an error detector to generate and compare linear and flexible SEDC for input of various bits, thereby detecting errors in addition/subtraction operations. CONSTITUTION: An input SEDC generator(100) receives binary input data and a carry-in bit. The input SEDC generator generates input SEDC which includes carry-out input SEDC and sum-out input SEDC corresponding to kinds of addition/deduction operations. An error detector(120) receives carry-out data and sum-out data and generates output SEDC which includes carry-out output SEDC and the sum-out output SEDC. The error detector outputs an error detection result by determining identity of the carry-out output SEDC and the carry-out input SEDC.
申请公布号 KR101268996(B1) 申请公布日期 2013.05.29
申请号 KR20120021150 申请日期 2012.02.29
申请人 INDUSTRY-ACADEMIC COOPERATION FOUNDATION, CHOSUN UNIVERSITY 发明人 LEE, JEONG A;SOMASUNDARAM NATARAJAN
分类号 G06F11/28;G06F11/07;G06F11/10 主分类号 G06F11/28
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