发明名称 |
Arithmetic processing unit, information processing device, and control method |
摘要 |
<p>An arithmetic processing unit (10) includes a first cache memory unit (20a) that holds a part of data stored in the storage device; an address register (37) that holds an address;a flag register (31a) that stores flag information;a decoding unit (3B) that decodes a prefetch instruction for acquiring data stored at the address in the storage device; and an instruction execution unit(38a) that executes a cache hit check instruction instead of the prefetch instruction on the basis of a decoded result when the flag information is held, the cache hit check instruction allowing for searching the first cache memory unit (20a) with the address to thereby make a first cache hit determination that the first cache memory unit (20a) holds the data stored at the address in the storage device.</p> |
申请公布号 |
EP2339453(B1) |
申请公布日期 |
2013.05.29 |
申请号 |
EP20100196437 |
申请日期 |
2010.12.22 |
申请人 |
FUJITSU LIMITED |
发明人 |
YAMAZAKI, IWAO;IMAI, HIROYUKI |
分类号 |
G06F9/38;G06F9/30;G06F9/318;G06F12/08 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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