Isolation circuitry and method for hiding a power consumption characteristic of an associated processing circuit

摘要

An isolation circuitry and method are provided for coupling between a power supply and processing circuitry in order to provide power to the processing circuitry whilst hiding a power consumption characteristic of that processing circuitry. The isolation circuitry comprises a plurality of sub-circuits, with each sub-circuit comprising a capacitor, a first switch configured to provide a first connection between the capacitor and the power supply, a second switch configured to provide a second connection between the capacitor and the processing circuitry, and a third switch configured to provide a third connection across the capacitor to partially discharge the capacitor. Control circuitry controls the plurality of sub-circuits, such that within each sub-circuit the first switch, second switch and third switch are placed in an active state in a repeating sequence. Each of the plurality of sub-circuits further comprises a comparator configured to place the third switch in an open state when a predetermined non-zero voltage difference across the capacitor is reached during the active state of the third switch. By such an approach, it is ensured that the voltage across the comparator at the end of the discharge operation is always the same irrespective of the voltage present at the start of the discharge operation. As a result, the power consumption characteristic of the processing circuitry is entirely hidden by the isolation circuitry. Further, the isolation circuitry of the present invention provides a particular power efficient mechanism for hiding the power consumption characteristic of the processing circuitry.