发明名称 |
Variable delay circuit and delay-locked loop including the same |
摘要 |
The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.
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申请公布号 |
US8451970(B2) |
申请公布日期 |
2013.05.28 |
申请号 |
US201113035093 |
申请日期 |
2011.02.25 |
申请人 |
KIM CHUL WOO;KWAK YOUNG HO;KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION |
发明人 |
KIM CHUL WOO;KWAK YOUNG HO |
分类号 |
H03D3/24;H03L7/00;H03L7/06;H04L7/00;H04L25/40 |
主分类号 |
H03D3/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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