| 摘要 |
A method (and computer program) identify shapes and locations of transistor elements within a geometric circuit layout. The transistor elements include an active area, at least one gate conductor and other transistor elements. Also, the gate conductor has sides running in a first direction, and has a width dimension running in a second direction perpendicular to the first direction. The method defines regions within the geometric circuit layout. To do so, the method defines a first region having a perimeter positioned along the sides of the gate conductor where the gate conductor intersects the active area and then expands the perimeter of the first region in the second direction to edges of the active area to define a perimeter of a second region. The first region and the second share perimeters in the first direction. The method then expands the perimeter of the second region in the first direction to define a perimeter of a third region. The second region and the third region share perimeters in the second direction. The method then separately evaluates effects the other transistor elements have within each of the first region, the second region, and the third region, to determine a characteristic of the gate conductor.
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