发明名称 Method of manufacturing semiconductor device including wiring layout and semiconductor device
摘要 A method of manufacturing a semiconductor device having a first wiring layer, a first interlayer insulating film, a second interlayer insulating film, a third interlayer insulating film, and a second wiring layer, in which the method includes depositing the second wiring layer on the third interlayer insulating film and, where the widths of first wiring layer and the second wiring layer are 10.0 mum or greater, executing one of etching the second wiring layer to set a width of 1.0 mum or greater in a portion where the first wiring layer and the second wiring layer overlap and etching the second wiring layer to seta horizontal distance of 2.0 mum or greater between adjacent portions of the first wiring layer and the second wiring layer.
申请公布号 US8450858(B2) 申请公布日期 2013.05.28
申请号 US20100771067 申请日期 2010.04.30
申请人 TAKAHASHI TAKUYA;FUCHINO FUMIHIRO;KOHNO YUUICHI;MIYATA MASANORI;RICOH COMPANY, LTD. 发明人 TAKAHASHI TAKUYA;FUCHINO FUMIHIRO;KOHNO YUUICHI;MIYATA MASANORI
分类号 H01L23/48;H01L23/52 主分类号 H01L23/48
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