发明名称 |
Apparatus for storing a data value in a retention mode |
摘要 |
Apparatus for storing a data value in the form of a master-slave latch supporting zig-zag power gating is described. A NAND gate 52 at the output of the latch forces a predetermined retention signal value at the output from the latch during a retention mode. A scan multiplexer 42 at the input to the latch selects the scan input, which is the predetermined retention signal from another latch, during the retention mode. Within the latch power gated circuitry 32 is subject to zig-zag power gating using virtual power rails VDDZ and VSSZ so as to reduce the leakage current. State storing circuitry 34 is permanently connected to the power supplies VDDG, VSSG such that it is able to maintain whatever signal value is stored therein during the retention mode.
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申请公布号 |
US8451039(B2) |
申请公布日期 |
2013.05.28 |
申请号 |
US201113067183 |
申请日期 |
2011.05.13 |
申请人 |
MYERS JAMES EDWARD;BIGGS JOHN PHILIP;FLYNN DAVID WALTER;TRADOWSKY CARSTEN;ARM LIMITED |
发明人 |
MYERS JAMES EDWARD;BIGGS JOHN PHILIP;FLYNN DAVID WALTER;TRADOWSKY CARSTEN |
分类号 |
H03K3/289 |
主分类号 |
H03K3/289 |
代理机构 |
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主权项 |
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地址 |
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