| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an integrated circuit that suppresses a variation in circuit threshold voltage while suppressing an increase in circuit delay. <P>SOLUTION: An integrated circuit 1 includes: a PMOS transistor MP1 connected between a high potential side power supply VDD and an output terminal OUT; an NMOS transistor MN1 connected between a low potential side power supply VSS and the output terminal OUT; a PMOS transistor MP2 and an NMOS transistor MN3 connected in series between the high potential side power supply VDD and the output terminal OUT; and an NMOS transistor MN2 and a PMOS transistor MP3 connected in series between the low potential side power supply VSS and the output terminal OUT. Gates of the PMOS transistors MP1, MP2 and the NMOS transistors MN1, MN2 are connected to an input terminal IN. A gate of the NMOS transistor MN3 is connected to the high potential side power supply, and a gate of the PMOS transistor MP3 is connected to the low potential side power supply. <P>COPYRIGHT: (C)2013,JPO&INPIT |
