发明名称 THREE-DIMENSIONAL INTEGRATED CIRCUIT HAVING REDUNDANT RELIEF STRUCTURE FOR CHIP BONDING SECTION
摘要 A chip is layered on a rewiring member. A plurality of connecting members and a plurality of redundant connecting members are arranged in the chip, and electrically connect the chip to the rewiring member. Redundant circuits are embedded in each of the rewiring member and the chip. When one of the connecting members is faulty, the redundant circuits cause one of the redundant connecting members to transmit a signal between the rewiring member and the chip, instead of the faulty connecting member. The connecting members have first and second subsets arranged in first and second regions, respectively. A distance between the rewiring member and the chip exceeds a predetermined threshold value in the first region in contrast to the second region. The first subset has a higher proportion of connecting members that the redundant circuits can replace with a subset of the redundant connecting members than the second subset.
申请公布号 US2013127028(A1) 申请公布日期 2013.05.23
申请号 US201213812011 申请日期 2012.01.11
申请人 MORIMOTO TAKASHI;HASHIMOTO TAKASHI 发明人 MORIMOTO TAKASHI;HASHIMOTO TAKASHI
分类号 H01L23/495 主分类号 H01L23/495
代理机构 代理人
主权项
地址