EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS-FIELD ARITHMETIC,申请号WO2012US44735-传众专利搜索

发明名称	EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS-FIELD ARITHMETIC
摘要	Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.
申请公布号	WO2013006388(A3)	申请公布日期	2013.05.23
申请号	WO2012US44735	申请日期	2012.06.28
申请人	INTEL CORPORATION;RADHAKRISHNAN, SIVAKUMAR;SCHMISSEUR, MARK A.;TAN, SIN S.;HAREN, KENNETH C.;BROWN, THOMAS C.;KUMAR, PANKAJ;GOPAL, VINODH;FEGHALI, WAJDI K.	发明人	RADHAKRISHNAN, SIVAKUMAR;SCHMISSEUR, MARK A.;TAN, SIN S.;HAREN, KENNETH C.;BROWN, THOMAS C.;KUMAR, PANKAJ;GOPAL, VINODH;FEGHALI, WAJDI K.
分类号	G06F11/10	主分类号	G06F11/10
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