发明名称 |
METHOD, APPARATUS AND SYSTEM FOR MEMORY VALIDATION |
摘要 |
<p>Techniques and mechanisms for assuring that one or more addressable locations in memory of a computer platform are transitioned from potentially invalid state to known-valid state. In an embodiment, a memory validation agent separate from a processor of the computer platform performs memory validation writes in response to an indication of power state transition. In another embodiment, the memory validation agent determines information to be included in write commands which implement the memory validation, where the determining the information is decoupled from operation of the processor.</p> |
申请公布号 |
WO2013074107(A1) |
申请公布日期 |
2013.05.23 |
申请号 |
WO2011US61248 |
申请日期 |
2011.11.17 |
申请人 |
INTEL CORPORATION;CHEW, YEN HSIANG |
发明人 |
CHEW, YEN HSIANG |
分类号 |
G06F12/00;G06F13/14;G11C7/10 |
主分类号 |
G06F12/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|