| 摘要 |
<P>PROBLEM TO BE SOLVED: To avoid occurrence of a linearity difference. <P>SOLUTION: A TG (timing generator) 40 includes a plurality of phase selectors 42 for selecting an arbitrary rise edge and a fall edge from timing of a multilayer clock generated by a multilayer clock generator 41 and outputting respective driving signals of the arbitrary phase. The phases of the respective driving signals can be set from a control section 70 and the phases required for the respective driving signals can be set. Thus, the phase of sample hold timing of respective analog signals by sample-and-hold circuits 12 an 22 on an F side and an L side (a plurality of ch) can be adjusted. Consequently, the control section 70 can adjust the sample-and-hold timing of the respective analog signals with the TG 40 so that the levels of the respective digital signals from A/D converters 14 on the F side and the L side are matched. <P>COPYRIGHT: (C)2013,JPO&INPIT |
