发明名称 |
CDR with digitally controlled lock to reference |
摘要 |
<p>In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation.</p> |
申请公布号 |
EP2571164(A3) |
申请公布日期 |
2013.05.22 |
申请号 |
EP20120184691 |
申请日期 |
2012.09.17 |
申请人 |
LSI CORPORATION |
发明人 |
SINDALOVSKY, VLADIMIR;SMITH, LANE A.;HARDY, BRETT D.;KUENG, JEFFREY S. |
分类号 |
H03L7/087;H03L7/091 |
主分类号 |
H03L7/087 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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