| 摘要 |
Techniques are disclosed herein for efficiently operating memory arrays of non-volatile storage devices. In one embodiment, when reading data from an MLC block, reading is sped up by not discharging bit lines between successive sensing operations. For example, all even bit lines are charged up and odd bit lines are grounded to set up sensing of memory cells that are associated with a first word line and the even bit lines. Then, memory cells associated with the first word line and the even bit lines are read by, for example, sensing the even bit lines. Then, while the even bit lines are still charged, memory cells associated with another word line and the even bit lines are read. Because the even bit lines remain charged between the two sensing operations, time is saved in not having to re-charge the bit lines to an appropriate level for sensing. |
