发明名称 Analog/digital partitioning of circuit designs for simulation
摘要 For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.
申请公布号 US8448116(B2) 申请公布日期 2013.05.21
申请号 US20100873162 申请日期 2010.08.31
申请人 CHETPUT CHANDRASHEKAR L.;KOLPEKWAR ABHIJEET;IYENGAR SRINIVASAN;CADENCE DESIGN SYSTEMS, INC. 发明人 CHETPUT CHANDRASHEKAR L.;KOLPEKWAR ABHIJEET;IYENGAR SRINIVASAN
分类号 G06F17/50 主分类号 G06F17/50
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