| 摘要 |
A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the second voltage level is higher than the first voltage level. Level shifting circuit embodiments having two or more parallel coupled depletion mode transistors coupled to a high voltage source and further coupled to the output by an enhancement mode transistor, and an additional transistor coupled between a first signal and the output of the level shifting circuit where the first signal has the same logic level of the input are disclosed.
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