发明名称 |
Semiconductor memory device having memory block configuration |
摘要 |
A semiconductor device includes a semiconductor substrate having first and second edge lines, address pads along the first edge line, and memory mats, each including normal memory blocks and a spare memory block. Each normal memory block has nonvolatile memory cells and is a unit of batch erase. The memory mats are arranged in a U-shaped area having a hollow portion facing the second edge line. The device includes column decoders arranged correspondingly to the memory mats, an analog/logic circuit arranged in the hollow portion, and a power supply pad arranged between the analog/logic circuit and the second edge line. The analog/logic circuit includes a charge pump circuit. The device further includes a first power supply interconnection supplying power supply voltage to the charge pump circuit from the power supply pad, and a second power supply interconnection supplying power supply voltage to the column decoder from the power supply pad.
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申请公布号 |
US8446765(B2) |
申请公布日期 |
2013.05.21 |
申请号 |
US201213481540 |
申请日期 |
2012.05.25 |
申请人 |
OGURA TAKU;YAMAUCHI TADAAKI;MITANI HIDENORI;KUBO TAKASHI;ARITOMI KENGO;RENESAS ELECTRONICS CORPORATION |
发明人 |
OGURA TAKU;YAMAUCHI TADAAKI;MITANI HIDENORI;KUBO TAKASHI;ARITOMI KENGO |
分类号 |
G11C11/34;G11C16/06;G11C5/02;G11C8/08;G11C11/00;G11C16/02;G11C16/16;G11C16/26;G11C29/00;G11C29/02;G11C29/04;G11C29/50 |
主分类号 |
G11C11/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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