发明名称 Method and system for reducing duty cycle distortion amplification in forwarded clocks
摘要 A method and apparatus for reducing the amplification of the duty cycle distortion of high frequency clock signals when is provided. A data signal is sent to a receiver via a first channel. A clock signal is sent to the receiver via a second channel. The clock signal is filtered to substantially remove therefrom low frequency components before the clock signal is used by the receiver to recover data from the data signal.
申请公布号 US8446985(B2) 申请公布日期 2013.05.21
申请号 US20080343426 申请日期 2008.12.23
申请人 DOBLAR DREW G.;HUANG DAWEI;SONG DEQIANG;ORACLE AMERICA, INC. 发明人 DOBLAR DREW G.;HUANG DAWEI;SONG DEQIANG
分类号 H03H7/30;H03H7/40;H03K5/159 主分类号 H03H7/30
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