Manufacturing features of different depth by placement of vias

摘要

A methodology for varying the depth of a design feature on a semiconductor wafer. Vias are formed according to design requirements. Nonfunctioning vias may also be placed at a location with respect to a design feature. After vias are formed, the semiconductor wafer is caused to undergo an ashing process followed by the application of an organic planarizing layer. The design features are then formed. If the depth of the design features does not meet design requirements, another semiconductor wafer may be processed to meet design requirements by varying the ashing conditions, choice of organic planarizing layer and/or the nonfunctioning and/or functioning via placement. Design features having various depths on a single semiconductor wafer may be formed with a single lithographic process.