Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred.
申请公布号
US8447930(B2)
申请公布日期
2013.05.21
申请号
US20100820528
申请日期
2010.06.22
申请人
BERGER DEANNA P.;FEE MICHAEL F.;JONES CHRISTINE C.;ORF DIANA L.;SONNELITTER, III ROBERT J.;INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人
BERGER DEANNA P.;FEE MICHAEL F.;JONES CHRISTINE C.;ORF DIANA L.;SONNELITTER, III ROBERT J.