发明名称 Method to reduce delay variation by sensitivity cancellation
摘要 A method receives an initial circuit design. The circuit design includes at least one path having at least one beginning point comprising a source, at least one ending point comprising a sink, and one or more circuit elements between the source and the sink. The method evaluates timing performance parameter sensitivities to manufacturing variations of each of the elements to identify how much each element will increase or decrease the timing performance parameter of the path for each change in each manufacturing variable associated with manufacturing the elements. Further, the method alters the elements within the path until elements that produce positive changes to the timing performance parameter for a given manufacturing variable change approximately equals (in magnitude) elements that produce negative changes to the timing performance parameter for the given manufacturing variable change, to produce an altered circuit design.
申请公布号 US8448110(B2) 申请公布日期 2013.05.21
申请号 US20090625139 申请日期 2009.11.24
申请人 HABITZ PETER A.;FOREMAN ERIC A.;TELLEZ GUSTAVO E.;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 HABITZ PETER A.;FOREMAN ERIC A.;TELLEZ GUSTAVO E.
分类号 G06F17/50;G06F9/455 主分类号 G06F17/50
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