发明名称 |
System and method for metastability verification of circuits of an integrated circuit |
摘要 |
A method and system for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized.
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申请公布号 |
US8448111(B2) |
申请公布日期 |
2013.05.21 |
申请号 |
US20110986644 |
申请日期 |
2011.01.07 |
申请人 |
MNEIMNEH MAHER;SARWARY SHAKER;JAIN PARAS MAL;BANSAL ASHISH;MOVAHED-EZAZI MOHAMMAD;GUPTA NAMIT;ATRENTA, INC. |
发明人 |
MNEIMNEH MAHER;SARWARY SHAKER;JAIN PARAS MAL;BANSAL ASHISH;MOVAHED-EZAZI MOHAMMAD;GUPTA NAMIT |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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