| 摘要 |
<P>PROBLEM TO BE SOLVED: To perform operation using a reference latency and an offset latency by a small-scale logical circuit. <P>SOLUTION: A semiconductor device comprises: a logic circuit 100 that logically synthesizes, for example, each of a plurality of bits A0 to A3 that indicate the value of a reference latency CL and each of a plurality of bits C0 to C2 that indicate the value of an offset latency SRL, and generates a plurality of control signals E0 to E3; and a logic circuit 200 that decodes the plurality of control signals E0 to E3 and generates a plurality of control signals ULPCL4 to ULPCL15. Thus, operation of the values of the reference latency CL and offset latency SRL is performed before decoding, thereby allowing an adjustment latency ULPCL to be calculated by using a smaller-scale logic circuit. <P>COPYRIGHT: (C)2013,JPO&INPIT |
