发明名称 PACKAGE SUBSTRATE IN WHICH VIA HOLE INTERMEDIATE LAYER IS EMBEDDED AND MANUFACTURING METHOD THEREOF
摘要 <P>PROBLEM TO BE SOLVED: To provide a package substrate in which a via hole intermediate layer is embedded and a manufacturing method thereof. <P>SOLUTION: A package substrate in which a via hole intermediate layer is embedded comprises: a mold seal layer 22; a via hole intermediate layer 20 embedded in the mold seal layer and having a plurality of conductive via holes 200; a re-wiring layer 21 embedded in the mold seal layer, provided in the via hole intermediate layer, and electrically connected to one end surface of the conductive via hole; and a build-up structure 23 provided in the mold seal layer and the via hole intermediate layer and electrically connected to the other end surface of the conductive via hole. Embedding the via hole intermediate layer in the mold seal layer causes the re-wiring layer to be electrically connected to an electrode pad of a relatively small semiconductor chip and the other end to be electrically connected to a conductive blind via hole of a relatively large build-up structure. This connection also causes a package substrate 2 to be connected to a semiconductor chip having a high wiring density. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013098526(A) 申请公布日期 2013.05.20
申请号 JP20120011761 申请日期 2012.01.24
申请人 KINKO DENSHI KOFUN YUGENKOSHI 发明人 KO TEKIGUN;SO SHISHO
分类号 H01L23/12 主分类号 H01L23/12
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