| 摘要 |
<P>PROBLEM TO BE SOLVED: To enhance a power source and GND of an I/O system and a non-I/O system of a semiconductor device in a well-balanced manner to improve low-voltage operation performance and high-speed operation performance. <P>SOLUTION: A semiconductor device comprises a wiring board 2 with one surface being formed so as to surround rows of connection pads 6A. The wiring board 2 includes a VSS planar conductor pattern 18 on the one surface, which is connected to a VSS connection pad 6A-1 via a distribution line 16. The wiring board 2 further includes on another surface, a VSSQ planar conductor pattern 21 arranged so as to link a plurality of VSSQ external terminals 7-3, and a VDDQ planar conductor pattern 22 arranged so as to link a plurality of VDDQ external terminals 7-4. <P>COPYRIGHT: (C)2013,JPO&INPIT |
