| 摘要 |
<P>PROBLEM TO BE SOLVED: To achieve both securing precision and holding a duty, in adjustment of clock skew in a clock tree. <P>SOLUTION: A layout device (10) is provided with a table where first cells each of which is formed of one stage of MOS transistors and second cell each of which is formed of a plurality of stages of MOS transistors are stored as libraries. The layout device includes an arithmetic unit (12) which can adjust clock skew between different clock systems in a clock tree by inserting combination chains comprising first cells and second cells, to the clock tree. By inserting the combination chains to adjust the clock skew, propagation of delay errors in individual first cells is suppressed to reduce delay errors in delay calculation. Further, since each first cell is formed of one stage of MOS transistors and the logic is inverted in the first cell, the layout device is advantageous with respect to holding a duty. <P>COPYRIGHT: (C)2013,JPO&INPIT |
