| 摘要 |
A chip package includes: a substrate having a first surface, a second surface, and a side surface connecting the first and the second surfaces; a dielectric layer located on the first surface; conducting pads comprising a first and a second conducting pads located in the dielectric layer; openings extending from the second surface towards the first surface and correspondingly exposing the conducting pads, wherein a first opening of the openings and a second opening of the openings next to the first opening respectively expose the first and the second conducting pads and extend along a direction intersecting the side surface of the substrate to respectively extend beyond the first and the second conducting pads; and a first and a second wire layers located on the second surface and extending into the first the second openings to electrically contact with the first and the second conducting pads, respectively. |
