| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an integrated circuit including a scan test circuit and another circuit to be tested using the scan test circuit. <P>SOLUTION: The scan test circuit includes a clock area bypass circuit configured to selectively bypass at least one scan chain having a plurality of sub-chains related to individual clock areas, and one or a plurality of sub-chains. The scan chain is configured to form a series shift register including some of all the sub-chains in operation in a scan shift mode, and one of the remaining sub-chains is bypassed by the clock area bypass circuit not to be a part of the series shift register in the scan shift mode. The clock area bypass circuit serves to shorten a test time of a scan test period and to reduce the power consumption by selectively bypassing a part of the scan chain related to a specific clock area. <P>COPYRIGHT: (C)2013,JPO&INPIT |
