发明名称 APPARATUS AND METHOD FOR FAST PHASE LOCKED LOOP(PLL) SETTLING FOR CELLULAR TIME-DIVISION DUPLEX(TDD) COMMUNICATIONS SYSTEMS
摘要 <p>PURPOSE: An apparatus for stabilizing a PLL[Phase Locked Loop]and a method thereof are provided to perform calibration of PLL when a communication device transfers a first operation mode to a second operation mode. CONSTITUTION: A standard PLL(108) provides a target signal. A controller(120) corrects the standard PLL by following the target signal with the standard signal when a communication device transfers a first operation mode to a second operation mode. The controller corrects the standard PLL by controlling a target frequency in a predetermined value. The predetermined value shows the previously known shifting of the target signal which is generated from a transition between the first operation mode and the second operation mode. [Reference numerals] (104) Oscillator; (106) Scaling module; (108) Reference phase-locked loop; (116) Transmitter; (118) Receiver; (120) Controller</p>
申请公布号 KR20130049761(A) 申请公布日期 2013.05.14
申请号 KR20120124360 申请日期 2012.11.05
申请人 BROADCOM CORPORATION 发明人 HARALABIDIS NIKOLAOS
分类号 H04L25/02;H03L7/06 主分类号 H04L25/02
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