发明名称 |
Rate-scalable, multistage quasi-cyclic LDPC coding |
摘要 |
Encoding is performed by dividing a quasi-cyclic low-density parity-check (QC-LDPC) parity check matrix into a first sub-matrix and a second sub-matrix. The first sub-matrix includes a plurality of circulant vectors and the plurality of circulant vectors is associated with a circulant size. Input data is received having a length which is a product of an integer multiplier and the circulant size. A first stage of multi-stage LDPC encoding is performed using the input data and a subset of the plurality of circulant vectors; the number of circulant vectors in the subset equals the integer multiplier.
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申请公布号 |
US8443257(B1) |
申请公布日期 |
2013.05.14 |
申请号 |
US201113039068 |
申请日期 |
2011.03.02 |
申请人 |
ZENG LINGQI;KOU YU;NG KIN MAN;YEUNG KWOK W.;SK HYNIX MEMORY SOLUTIONS INC. |
发明人 |
ZENG LINGQI;KOU YU;NG KIN MAN;YEUNG KWOK W. |
分类号 |
H03M13/00 |
主分类号 |
H03M13/00 |
代理机构 |
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