发明名称 |
Disparate clock domain synchronization |
摘要 |
Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized. |
申请公布号 |
US8442075(B2) |
申请公布日期 |
2013.05.14 |
申请号 |
US201113071938 |
申请日期 |
2011.03.25 |
申请人 |
TO HING (THOMAS) YAN;LEMOS GREGORY;INTEL CORPORATION |
发明人 |
TO HING (THOMAS) YAN;LEMOS GREGORY |
分类号 |
H04J3/06;H03L7/06 |
主分类号 |
H04J3/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|