发明名称 Mat compress circuit and semiconductor memory device having the same
摘要 A mat compress circuit includes a pre-control signal generator that generates a first pre-control signal and a second pre-control signal alternatively activated in response to an up/down bank selection address in a mat compression test, and a control signal transmitter that inverts and transfers the first and second pre-control signals in response to a switching signal activated when there is an input of a block selection address in the mat compression test.
申请公布号 US8441875(B2) 申请公布日期 2013.05.14
申请号 US20090650717 申请日期 2009.12.31
申请人 CHOI YOUNG GEUN;HYNIX SEMICONDCUTOR INC. 发明人 CHOI YOUNG GEUN
分类号 G11C7/00 主分类号 G11C7/00
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