| 摘要 |
Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed. |
