发明名称 |
Semiconductor memory devices including burn-in test circuits |
摘要 |
A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed. |
申请公布号 |
US8441877(B2) |
申请公布日期 |
2013.05.14 |
申请号 |
US20100731749 |
申请日期 |
2010.03.25 |
申请人 |
CHOI JONG-HYUN;KANG SANG-SEOK;SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHOI JONG-HYUN;KANG SANG-SEOK |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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