发明名称 |
Techniques for cache injection in a processor system responsive to a specific instruction sequence |
摘要 |
A technique for performing cache injection includes monitoring an instruction stream for a specific instruction sequence. Addresses on a bus are then monitored, at a cache, in response to detecting the specific instruction sequence a determined number of times. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache. |
申请公布号 |
US8443146(B2) |
申请公布日期 |
2013.05.14 |
申请号 |
US20080212961 |
申请日期 |
2008.09.18 |
申请人 |
ARIMILLI LAKSHMINARAYANA BABA;ARIMILLI RAVI K.;SINHAROY BALARAM;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ARIMILLI LAKSHMINARAYANA BABA;ARIMILLI RAVI K.;SINHAROY BALARAM |
分类号 |
G06F12/00;G06F13/00;G06F13/28 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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