发明名称 |
PLL using interpolative divider as digitally controlled oscillator |
摘要 |
One or more PLLs are formed on an integrated circuit. Each PLL includes an interpolative divider configured as a digitally controlled oscillator, which receives a reference clock signal and supplies an output signal divided according to a divide ratio. A feedback divider is coupled to the output signal of the interpolative divider and supplies a divided output signal as a feedback signal. A phase detector receives the feedback signal and a clock signal to which the PLL locks. The phase detector supplies a phase error corresponding to a difference between the clock signal and the feedback signal and the divide ratio is adjusted according to the phase error. |
申请公布号 |
US8441291(B2) |
申请公布日期 |
2013.05.14 |
申请号 |
US201113243149 |
申请日期 |
2011.09.23 |
申请人 |
HARA SUSUMU;ELDREDGE ADAM B.;FU ZHUO;WILSON JAMES E.;SILICON LABORATORIES INC. |
发明人 |
HARA SUSUMU;ELDREDGE ADAM B.;FU ZHUO;WILSON JAMES E. |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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