| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a non-volatile memory capable of switching a high-speed operation and a low-speed operation and reducing power consumption during the low-speed operation more than before. <P>SOLUTION: In a semiconductor device 1, a clock generation circuit 40 generates a clock whose frequency during a high frequency mode is higher than the frequency during a low frequency mode. A central processing unit 20 obtains reading data read from a non-volatile memory 10 via a data bus 11. A clock delay section 50A includes a first path 51 via a plurality of stages of buffers 55 in a cascade connection and a second path 52 that bypasses the plurality of stages of buffers 55. The clock delay section 50A supplies a clock from the clock generation circuit 40 to the central processing unit 20 via the first path 51 during the high frequency mode and a clock from the clock generation circuit 40 to the central processing unit 20 via the second path 52 during the low frequency mode. <P>COPYRIGHT: (C)2013,JPO&INPIT |
