SEMICONDUCTOR TEST DEVICE AND ADDRESS SCRAMBLE GENERATING METHOD THEREOF

摘要

PURPOSE: A semiconductor test device and an address scramble generating method thereof are provided to prevent a human error by automatically generating an address scramble. CONSTITUTION: Block structure information and address information corresponding to a semiconductor memory device are received(S10). A physical address is aligned with a hexadecimal based on the address information and a logic address of the hexadecimal(S20). An address scramble logical expression which includes the logic address corresponding to the physical address is generated based on the address information(S50). The generated address scramble logical expression is minimized by using a preset algorithm(S60). [Reference numerals] (AA) Start; (BB) End; (S10) Receive block structure information and address information corresponding to a semiconductor memory device; (S20) Align a physical address with a hexadecimal based on the address information and an inputted logic address; (S30) Calculate a partial address area based on the aligned address information with the hexadecimal; (S40) Realign the logic address included in the partial address area and convert the physical address and the realigned logic address with a binary number; (S50) Generate an address scramble logical expression; (S60) Minimize the generated address scramble logical expression using a preset algorithm