MEMORY CONTROLLER AND DATA STORAGE DEVICE

摘要

An estimated cell error rate CERest is set on the basis of an estimated retention time Tret determined from a calculated bit error rate BER, a number of rewrites NW/E, data of a target cell Datatag, and data of a memory cell peripheral to the target cell Dataadj (Step S230); an upper-level page LLRu and a lower-level page LLRl are set for all the bits in a page of data read out using the estimated cell error rate CERest that has been set (Step S250), and the upper-level page LLRu and the lower-level page LLRl set in this manner are used to perform error correction and decoding for data read out from a flash memory (22). This makes it possible to minimize any increase in processing time while enhancing error correction capabilities.