发明名称 |
Method and Apparatus for Simulating Gate Capacitance of a Tucked Transistor Device |
摘要 |
A method for simulating a tucked transistor device having a diffusion region defined in a semiconductor layer, a gate electrode adjacent a first side of the diffusion region, a floating gate electrode adjacent a second side of the diffusion region, and an isolation structure disposed beneath at least a portion of the floating gate electrode is provided. The method includes receiving a first netlist having an entry for the tucked transistor device in a computing apparatus. The entry defines parameters associated with the gate electrode and the diffusion region. A parasitic capacitance component is added to the entry representing a gate capacitance between the floating gate and the diffusion region in the computing apparatus.
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申请公布号 |
US2013117001(A1) |
申请公布日期 |
2013.05.09 |
申请号 |
US201113288541 |
申请日期 |
2011.11.03 |
申请人 |
GOO JUNG-SUK;THURUTHIYIL CIBY;RAMASUBRAMANIAN VENKAT;FARICELLI JOHN;ADVANCED MICRO DEVICES, INC.;GLOBALFOUNDRIES INC. |
发明人 |
GOO JUNG-SUK;THURUTHIYIL CIBY;RAMASUBRAMANIAN VENKAT;FARICELLI JOHN |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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