A DELAY LOCKED LOOP

摘要

PURPOSE: A delay locked loop is provided to reduce the maximum static phase offset. CONSTITUTION: A delay locked loop includes a delay signal generation unit(100), a phase synthesis unit(200) and a phase detection unit(300). The delay signal generation unit delays a first delay signal having a first phase and a second delay signal having a second phase by delaying a reference signal based on a delay control signal. The phase synthesis unit generates a third signal having a third phase using the first delay signal and the second delay signal. The phase detection unit generates a control code by comparing the first, the second, and the third delay signals with the reference signal. [Reference numerals] (110) First fine delay line; (120) Second fine delay line; (200) Phase synthesis unit; (310) First detection unit; (320) Second detection unit; (330) Third detection unit; (400) Phase control signal generation unit; (500) Delay control signal generation unit; (600) First MUX; (700) Second MUX; (800) Coarse delay line