| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a level shift circuit that has a small footprint, retards effects of temperature changes and element variations, and implements a high quality level shift by reducing noise. <P>SOLUTION: A level shift circuit 1 mainly includes: a level shift section 10 for level-shifting a first signal (V<SB POS="POST">IN</SB>) to output a second signal (V<SB POS="POST">m</SB>); and an output buffer section 30 including a CMOS inverter circuit section 32 that includes a pMOS transistor 32a and an nMOS transistor 32b and inverts the second signal to output a third signal (S<SB POS="POST">1</SB>), a delay circuit section 33 that includes an even number of inverter elements (first inverter 33a to m-th inverter 33m) and delays the third signal to generate a fourth signal (S<SB POS="POST">3</SB>), a logic circuit section 34 that includes a logic element and receives the third signal and the fourth signal to output a fifth signal (S<SB POS="POST">5</SB>), and a D-FF element 35 that receives the fourth signal and the fifth signal. <P>COPYRIGHT: (C)2013,JPO&INPIT |
