| 摘要 |
A method of controlling a vertical dual-gate DRAM provides a short circuit state, a clearing state and a false broken circuit state. In the short circuit state, a first gate and a second gate at two sides of a first pillar are controlled to respectively have a turn-on voltage to form electric connection between a drain and a source at two ends of the first pillar. In the clearing state, the first gate and second gate are controlled to respectively have a clearing voltage to disconnect electric connection between the drain and source at two ends of the first pillar. The false broken circuit state is entered after the clearing state has been finished. The invention does not separate gates between neighboring pillars, but controls ON/OFF of transistors electrically so that no current leakage is generated in the clearing state and problem of inaccurate data reading can be prevented.
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