发明名称 N-way parallel turbo decoder architecture
摘要 Various embodiments relate to a memory device in a turbo decoder and a related method for allocating data into the memory device. Different communications standards use data blocks of varying sizes when enacting block decoding of concatenated convolutional codes. The memory device efficiently minimizes space while enabling a higher throughput of the turbo decoder by enabling a plurality of memory banks of equal size. The number of memory banks may be limited by the amount of unused space in the memory banks, which may be a waste of area on an IC chip. Using the address associated with the maximum value of the data block, the memory may be split into a plurality of memory blocks according to the most-significant bits of the maximum address, with a number of parallel SISO decoders matching the number of memory banks. This may enable higher throughput while minimizing area on the IC chip.
申请公布号 US8438434(B2) 申请公布日期 2013.05.07
申请号 US20090650072 申请日期 2009.12.30
申请人 ENGIN NUR;NXP B.V. 发明人 ENGIN NUR
分类号 G06F11/00 主分类号 G06F11/00
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