发明名称 Memory controller and memory system using the same
摘要 According to an aspect of embodiment, a memory controller for controlling a memory having areas of data unit of K bits, includes a data mapping unit dividing N bits of data, where N is not a multiple of K, into K bits and (N-K) bits, and in regard to L pieces of the data, arranging L K-bit data into L data units, and arranging L (N-K)-bit data into M (M=L×(N-K)/K) data units by packing; and an access control unit access-controlling the memory to access the L K-bit data as L data units, and access-controlling the memory to access the packed L (N-K)-bit data as M data units.
申请公布号 US8436865(B2) 申请公布日期 2013.05.07
申请号 US20100877574 申请日期 2010.09.08
申请人 WATANABE YASUHIRO;FUJITSU LIMITED 发明人 WATANABE YASUHIRO
分类号 G09G5/39;G06T1/60 主分类号 G09G5/39
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