发明名称 Method for testing an address bus in a logic module
摘要 In a method for testing an address bus in a logic module, a logic module, a computer program and a computer program product, the method provides for a logic module to have at least one data register, into which addresses detected by the address decoder are written.
申请公布号 US8438435(B2) 申请公布日期 2013.05.07
申请号 US20080738253 申请日期 2008.09.10
申请人 SCHNEIDER THOMAS;WIRTH PETER;PFITZER OTTO;ROBERT BOSCH GMBH 发明人 SCHNEIDER THOMAS;WIRTH PETER;PFITZER OTTO
分类号 G01R31/28 主分类号 G01R31/28
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