摘要 |
A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores, wherein at least one of a number of the processor cores, a size of each of the plurality of caches, or a size of each of the plurality of memories is configured for performing a reverse-time-migration (RTM) computation. |
申请人 |
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA;FRAUNHOFER-GESELLSCHAFT ZUR FORDERUNG DER ANGEWANDTEN FORSCHUNG E.V.;SHALF, JOHN;DONOFRIO, DAVID;OLIKER, LEONID;KRUEGER, JENS;WILLIAMS, SAMUEL |
发明人 |
SHALF, JOHN;DONOFRIO, DAVID;OLIKER, LEONID;KRUEGER, JENS;WILLIAMS, SAMUEL |