发明名称 DEVICE MATCHING LAYOUT AND METHOD FOR IC
摘要 The present invention relates to device matching in an integrated circuit. In one embodiment, an integrated circuit of matched devices can include: N main-devices to be matched by 4×K sub-devices configured to form K device arrays, where each of the device arrays includes four sub-device groups arrayed symmetrically around a vertical axis and a horizontal axis, where each of the sub-device groups includes N sub-devices arrayed with equal distance along a direction of the vertical axis, where K and N are integers, and N is larger than two; metal lead wires arrayed in parallel and with equal distance, and configured to connect the main-devices; a common connecting wire configured to connect common nodes of the sub-devices together; and where four sub-devices arrayed in the four sub-device groups, and other sub-devices arrayed in other sub-device groups, are coupled to form 4×K sub-devices to match the main-devices.
申请公布号 US2013105938(A1) 申请公布日期 2013.05.02
申请号 US201213633267 申请日期 2012.10.02
申请人 SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU);SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD 发明人 CHENG SHUAI
分类号 G06F17/50;H01L27/04 主分类号 G06F17/50
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