发明名称 |
CACHE MEMORY APPARATUS, CACHE CONTROL METHOD, AND MICROPROCESSOR SYSTEM |
摘要 |
A cache memory apparatus according to the present invention includes a cache memory that caches an instruction code corresponding to a fetch address and a cache control circuit that controls the instruction code to be cached in the cache memory. The cache control circuit caches an instruction code corresponding to a subroutine when the fetch address indicates a branch into the subroutine and disables the instruction code to be cached when the number of the instruction codes to be cached exceeds a previously set maximum number.
|
申请公布号 |
US2013111140(A1) |
申请公布日期 |
2013.05.02 |
申请号 |
US201213668009 |
申请日期 |
2012.11.02 |
申请人 |
RENESAS ELECTRONICS CORPORATION;RENESAS ELECTRONICS CORPORATION |
发明人 |
KITAHARA TAKASHI |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|