发明名称 |
Fractional digital PLL with analog phase error compensator |
摘要 |
Disclosed is a fractional digital phase locked loop with an analog phase error compensator. The digital phase locked loop with an analog phase error compensator can reduce excessive power consumption and power noise and transient current noise while increasing phase error detection resolution by performing fractional phase error detection and compensation through the analog phase error compensator. |
申请公布号 |
US8432199(B2) |
申请公布日期 |
2013.04.30 |
申请号 |
US201113310581 |
申请日期 |
2011.12.02 |
申请人 |
LEE JA YOL;KIM SEONG-DO;YU HYUN KYU;ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
LEE JA YOL;KIM SEONG-DO;YU HYUN KYU |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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